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Implimentation Of Multiplication Algorithm Using Vedic Multiplication: A Review

Publication Date : 04/05/2016



Author(s) :

Oswal S.M , Hon Y.S.


Conference Name :
International Conference on Recent Trends in Engineering and Technology



Abstract :

At present, it has been necessary to increase the speed of multiplier as the need of high speed processors is increasing. Multiplier is an important basic function in most fast processing system. Conventional processors need great hardware resources and take more time in multiplication operation. This paper presents high speed multiplier depending on vertical & crosswise method of Vedic mathematics. Implementation is carried on digital hardware. Vedic multiplication needs same number of addition and multiplication operations of normal multiplier using digital hardware; wherein mental calculation is the only case where it differs. Few VHDL codes have been programmed for the same. An efficient implementation of high speed multiplier using the Vedic multiplication method. In this we compare the working of the three multiplier by implementing each of them on FPGA Spartan3 board. As far as comparison is concerned, all multipliers have been tested for 8, 16 and 32 bits multiplications. In our project when we compare the path delay of all the multipliers we find that 8 bit and 16bit Urdhva algorithm gives 50% better delay than that of Nikhilam whereas 100% than that of Binary multiplier.. The result of work helps us to choose a better option between methods of vedic multiplier in fabricating different systems. Multipliers form one of the most important component of many systems. So by analyzing the working of different multipliers helps to frame a better system with less path delay.


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