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Implementation of DA based FIR 16 Order LPF using IP Core Generator

Publication Date : 10/07/2015

Author(s) :

Anisha Unnikrishnan , Manisha Ghortale , Ankita Aher , Mayuri Joshi.

Conference Name :
4th International Conference on Recent Trends in Engineering & Technology(ICRTET-2015) July 2-4,2015 Organized by SNJB's KBJ College of Engineering,Chandwad,Nashik,Maharashtra,India

Abstract :

This paper provides the principle of Distributed Arithmetic and introduces it into a FIR 16 order low-pass filter using IP core generator. The implementation of FIR filters on FPGA based on traditional method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. A new design and implementation of FIR filters using Distributed Arithmetic is provided to solve this problem. We can make a Look-Up-Table (LUT) to conserve the MAC values and callout the values according to the input data. The simulation results indicate that FIR filters using Distributed Arithmetic can work stable and can save almost less than 50 percent hardware recourses, and can be applied to a variety of areas for its great flexibility and high reliability. IP core generator methodology will reduce the time for design, generation, integration and testing of system.

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