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A Review on VLSI Implementation of Multiplierless FIR Filter Based On Distributed Arithmetic

Publication Date : 10/07/2015

Author(s) :

Komal Lineswala , Nishit Vankawala , Prof. Rakesh Gajre.

Conference Name :
4th International Conference on Recent Trends in Engineering & Technology(ICRTET-2015) July 2-4,2015 Organized by SNJB's KBJ College of Engineering,Chandwad,Nashik,Maharashtra,India

Abstract :

The main target for any design is to implement a digital system that has high speed, low power consumption and has low hardware usage and memory requirement. So, a detailed review on one of the high speed and area efficient multiplierless technique for realizing FIR filter based on Distributed Arithmetic (DA) is presented. Various architectures for implementing high order FIR filter based on DA which makes minimum usage of hardware. And also architecture for high speed FIR filter is reviewed which attains maximum speed at a cost of some hardware. However, using DA results up to 50% reduction in total occupied area compared to direct FIR filter implementation.

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