Call For Paper Volume:4 Issue:10 Oct'2017 |

Design and Implementation of 8×8 VEDIC Multiplier Using Submicron Technology

Publication Date : 07/03/2016



Author(s) :

RAVI S. PATEL , B.H.Nagpara , K.M.Pattani.


Volume/Issue :
Volume 3
,
Issue 2
(03 - 2016)



Abstract :

Multiplication is one of the basic operations for any high speed digital logic system design, digital signal processors or communication system. Primary issues in design of multiplier are area, delay, and power dissipation. There are many algorithms like booth multiplier, array multiplier, vedic multiplier, compressor based vedic multiplier for overcoming this problems. This paper mainly presents VEDIC multiplier using Urdhva Tiryagbhyam Sutra  and it uses Full Adder, Ripple Carry Adder, and basic gates. Keeping in mind that power dissipation and delay are the primary factors for multiplier and it should be improved in the design. The design has been implemented using 45nm CMOS technology at 1.0v supply voltage in LTSpice IV tool. The results are compared with previously reported papers. 


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Design and Implementation of 8×8 VEDIC Multiplier Using Submicron Technology

February 29, 2016