Call For Paper Volume:4 Issue:10 Oct'2017 |

Design of Sequential and Combinational Multipliers for comparing constraints at 130nm Technology

Publication Date : 06/08/2015



Author(s) :

VASUDEVA.G .


Volume/Issue :
Volume 2
,
Issue 8
(08 - 2015)



Abstract :

For many years VLSI chip designers have been using  Metal-oxide semiconductor field effect transistors(MOSFET).Designers have used MOSFET circuits in the designs because MOSFET use little power and they are cheaper to develop or fabricate. To satisfy the demands of making the chip smaller, the designers just simply shrink the dimensions to fit the circuit layouts. The shrinkage is also known as “Scaling”. Unfortunately, the continuous scaling of the circuit design will eventually cause problems in terms of area, timing and power. Signal processing is one of the most power hungry applications. Adders and Multipliers are the main building blocks for signal processing applications. Saving area, power and timing in adders and multipliers would reduce the area, power and timing significantly at the chip level .In this present investigation 3 multiplier structures are selected from existing multiplier types. The selected multipliers are Booth multiplier, Wallace tree multiplier and Dadda multiplier. Benchmarking for these 3 multipliers is done in terms of area, power and timing for 8 bits at 130nm technology. The HDL code for the selected multipliers is written in Verilog HDL and simulated in MODELSIM. To calculate the power and delay for these 3 multipliers we have used Design Compiler


No. of Downloads :

21


Indexing

Web Design MymensinghPremium WordPress ThemesWeb Development

Design of Sequential and Combinational Multipliers for comparing constraints at 130nm Technology

August 3, 2015