Call For Paper Volume:4 Issue:10 Oct'2017 |

REDUCING POWER CONSUMPTION USING CLOCK GATING TECHNIQUE IN FLIPFLOP

Publication Date : 07/06/2015



Author(s) :

RAJESWARI.S , ELAVARASI.P.


Volume/Issue :
Volume 2
,
Issue 6
(06 - 2015)



Abstract :

In this paper describes about reducing the power consumption of a synchronous digital system by minimizing the total power consumed by using the clock signals. To reducing the clock signals, gating techniques can be used. The synchronous design operates at highest frequency that derives a large load because it has to reach many sequential elements throughout the chip. Thus clock signals have been a great source of power dissipation because of high frequency and load. Clock signals do not perform any computation and mainly used for synchronization. Hence these signals are not carrying any information. So, by using clock gating one can save power by reducing unnecessary clock activities inside the gated module. A new counter using clock gated flip-flop is presented in this paper. The circuit is based on a new clock gating flip flop approach to reduce the signal’s switching power consumption. It has reduced the number of transistors. The proposed flip-flop is used to design the counter circuit.


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REDUCING POWER CONSUMPTION USING CLOCK GATING TECHNIQUE IN FLIPFLOP

June 5, 2015