Call For Paper Volume:4 Issue:9 Sep'2017 |

Design of Pulse Triggered Flip Flop Using Conditional Pulse Enhancement Technique

Publication Date : 07/06/2015



Author(s) :

P.NAVEENASINDHU , N.MANIKANDAN.


Volume/Issue :
Volume 2
,
Issue 6
(06 - 2015)



Abstract :

In this paper a low power and low area pulse triggered flip flop has been analyzed. The dominant part of this VLSI process design is power consumed by the clock. The flip flop is the basic element of memory element and clocked signal. The conventional TSPCFF is use to one extra NMOS transistor to shorten the delay and power. The conventional design removes the long discharging problem and reduces D to Q delay. Thus, the proposed design reduces the number of NMOS transistors stacked in the discharging path.  The proposed design is compared with the some conventional design EP-DCO, CDFF, TSPCFF. The schematic and post-layout simulations have been done using tanner tool at 250nm VLSI technology. The proposed design has resulted in reduction of overall power consumption in comparison to some conventional technique EP-DCO, CDFF, TSPCFF respectively. The results also show some reduction in leakage power. The average power consumption of proposed pulse triggered flip flop using pass transistor logic is 16uw and the number of transistors used 18.


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Design of Pulse Triggered Flip Flop Using Conditional Pulse Enhancement Technique

June 4, 2015