Call For Paper Volume:6 Issue:2 Feb'2019 |

Design Of Reversible Synchronous Sequential Circuits

Publication Date : 28/06/2015

Author(s) :

Sonawane Parag Narayan , Hatkar Arvind Pandurang.

Volume/Issue :
Volume 2
Issue 6
(06 - 2015)

Abstract :

In early 70`s one computer requires one whole room and now a days we kept commuter in our pockets, how this happens? This happens because we did tremendous revaluation in VLSI field. We rapidly decrease size of transistors. After decades of continuous improvements and shrinking feature sizes, the development of conventional computing technologies faces enormous challenges. In particular, power dissipation in today's computer chips becomes crucial. Reversible computation is a promising alternative to these technologies, where power dissipation can be reduced or even eliminated. Reversible logic has become very promising for low power design using emerging computing technologies. A number of good works have been reported on reversible combinational circuit design. However, only a few works reported on the design of reversible latches and flip-flops on the top of reversible combinational gates and suggested that sequential circuits be built by replacing the latches and flip-flops and associated combinational gates of the traditional irreversible designs by their reversible counter parts. This replacement technique is not very promising, because it leads to high quantum cost and garbage outputs. In this paper we design reversible synchronous sequential circuit such as counter. This design technique is directly from reversible gates using Pseudo Reed-Muller Expressions. This technique shows very much improved results In terms of quantum cost and garbage outputs.

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Design Of Reversible Synchronous Sequential Circuits

June 26, 2015