Call For Paper Volume:4 Issue:10 Oct'2017 |

HIGH PERFORMANCE FIR FILTER USING BIT-PAIR RECODED AND FUSED ADD-MULTIPLIER

Publication Date : 12/05/2015



Author(s) :

ARUNA DEVI.P.


Volume/Issue :
Volume 2
,
Issue 5
(05 - 2015)



Abstract :

DSP plays an important role in development of modern consumer electronics. Large number of arithmetic operations is carried out in DSP applications. To optimize the design of the fused Add-Multiply (FAM) operator for increasing performance, the technique - Bit pair recoding is implemented in FAM as direct recoding of the sum of two numbers. An efficient and structured recoding technique and their three different schemes by incorporating them in FAM designs are explored. The comparison of the three different schemes: Sum-to-Bit-pair recoding FAM design is performed and their significant reductions in terms of critical delay, hardware complexity and power consumption of the FAM unit is obtained. The delay present in the existing FAM design is overcome by faithfully rounding and Truncation method and the proposed design is finally implemented in FIR filter and their parameters are analyzed through FPGA.


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HIGH PERFORMANCE FIR FILTER USING BIT-PAIR RECODED AND FUSED ADD-MULTIPLIER

May 10, 2015