Call For Paper Volume:4 Issue:10 Oct'2017 |

Design of Asynchronous Viterbi Decoder Using Bundled Data Protocol for Low Power Consumption

Publication Date : 28/04/2015



Author(s) :

NUPUR R. CHAMBHARE , PROF. SUREKHA TADSE KALAMBE.


Volume/Issue :
Volume 2
,
Issue 4
(04 - 2015)



Abstract :

The main aim of this article is to design Asynchronous Viterbi Decoder in order to get low power consumption and increasing the speed. Fast developments in the stream of communication have increasing demands of low power and high speed decoders with low circuit implementation. In this paper, Asynchronous Viterbi Decoder has been implemented with code rate of r=1/3 and constraint length K=3 and the simulation results are operated by using VHDL in Model Sim SE 6.1f tool and 5.14mW power consumption is obtained. This paper also focuses on the study of different sections of Viterbi Decoder.  For the Asynchronous design, Bundled data protocol is used in this paper. Asynchronous designs have many benefits over the Synchronous designs. 


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Design of Asynchronous Viterbi Decoder Using Bundled Data Protocol for Low Power Consumption

April 27, 2015