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Analysis Of Double-Tail Comparator With Reduced Delay

Publication Date : 31/03/2015

Author(s) :

Dhivya Bharathi.M , Thilakavathi.S.

Volume/Issue :
Volume 2
Issue 3
(03 - 2015)

Abstract :

In Today’s emerging trends low power, small chip area plays an important factor which leads to use dynamic regenerative comparators in order to increase the speed and power efficiency. Different methods were used to reduce power consumption which will reduce the delay in the circuit. An analysis on the delay and analytical expressions can also be derived for dynamic comparators. These expressions results in delay and tradeoffs. In Proposed system for low power and fast operation in small supply voltages double-tail comparator is modified by adding few transistor where the positive feedback is strengthened which will reduce delay. Clock frequency is increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 v. The standard deviation of the input-referred offset is 7.8mv at 1.2 v supply.

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Analysis Of Double-Tail Comparator With Reduced Delay

March 2, 2015