Call For Paper Volume:4 Issue:10 Oct'2017 |

A Survey on the Architecture for an Efficient Memory Built in Self-Test For Configurable Embedded SRAM Memory

Publication Date : 31/03/2015



Author(s) :

NISHA O. S. , Dr.K. SIVA SANKAR.


Volume/Issue :
Volume 2
,
Issue 3
(03 - 2015)



Abstract :

Today’s submicron VLSI technology has been emerged as integration of many VLSI ICs into a single Si Chip called System-on-Chip (SoC). The SoC architecture normally contains multiple processors along with either separate or centralized memory blocks as its core elements as well as many noncore elements Due to the increased demands for high data storage, the integration of on-chip memories ranging from Gigabytes to Terrabytes is becoming essential for the latest SoC technology. To improve the reliability and performance of SoCs due to technology miniaturization and increased memory density, there is a need to incorporate on-chip self-testing unit for testing these memory units. Further, to improve the yield and fault tolerance of on-chip memories without degradation on its performance, self-repair mechanism may be integrated on chip


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A Survey on the Architecture for an Efficient Memory Built in Self-Test For Configurable Embedded SRAM Memory

February 19, 2015