Call For Paper Volume:4 Issue:10 Oct'2017 |

A NEW DATA ENCODER AND DECODER SCHEME FOR NETWORK ON CHIP

Publication Date : 28/02/2015



Author(s) :

DURAIMURUGAN , V.BHARATHI.


Volume/Issue :
Volume 2
,
Issue 2
(02 - 2015)



Abstract :

System-on-chip (soc) based system has so many disadvantages in power-dissipation as well as clock rate while the data transfer from one system to another system in on-chip. At the same time, a higher operated system does not support the lower operated bus network for data transfer. However an alternative scheme is proposed for high speed data transfer. But this scheme is limited to SOCs. Unlike soc, network-on-chip (NOC) has so many advantages for data transfer. It has a special feature to transfer the data in on-chip named as transitional encoder. Its operation is based on input transitions. At the same time it supports systems which are higher operated frequencies. In this project, a low-power encoding scheme is proposed.  The proposed system yields lower dynamic power dissipation due to the reduction of switching activity and coupling switching activity when compared to existing system. Even-though many factors which is based on power dissipation, the dynamic power dissipation is only considerable for reasonable advantage. The proposed system is synthesized using quartus II 9.1 software. Besides, the proposed system will be extended up to interlink PE communication with help of routers and PE’s which are performed by various operations. To implement this system in real NOC’s contains the proposed encoders and decoders for data transfer with regular traffic scenarios should be considered.


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A NEW DATA ENCODER AND DECODER SCHEME FOR NETWORK ON CHIP

March 1, 2015