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A High Speed and Low Voltage Dynamic Comparator for ADCs

Publication Date : 25/11/2015

Author(s) :

M.Balaji , G.Karthikeyan , R.Baskar , R.Jayaprakash.

Volume/Issue :
Volume 2
Issue 11
(11 - 2015)

Abstract :

A new dynamic comparator is proposed and it is compared with two existing comparators in terms of voltage, delay and frequency. CMOS dynamic comparator which has dual input, dual output inverter stage suitable for high speed ADCs with low voltage and low power dissipation. A conventional comparator is replaced with dynamic comparator which reduces the delay and voltage which increases the speed. The technology scaling of MOS transistors enables low voltage and low delay which decreases the offset voltage of the comparator. The proposed system has less number of voltage and delay when compared to other comparators. The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency.

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A High Speed and Low Voltage Dynamic Comparator for ADCs

November 23, 2015