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FPGA Implementation of High Speed Architecture of CSLA using D-Latches

Publication Date : 05/12/2014



Author(s) :

P.Sajid Khan , MD.Shamshad begum.


Volume/Issue :
Volume 1
,
Issue 6
(12 - 2014)



Abstract :

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in Xilinx 13.2 with reference to FPGA device XC3S500E.


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FPGA Implementation of High Speed Architecture of CSLA using D-Latches

December 2, 2014