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Power Reduction In Vlsi Systems By Using Multi-Bit Flip-Flops

Publication Date : 30/11/2014

Author(s) :

Sivakrishna Modiboyena , Kanumuri Koteswararao.

Volume/Issue :
Volume 1
Issue 5
(11 - 2014)

Abstract :

The utilization of power has turned into a smoldering issue in current VLSI design. Power consumption can be reduced by substituting some flip-flops with less multi-bit flip-flops. Multi-bit flip-flops are one of the strategies for reducing the clock power consumption. This project concentrates on reducing of clock force utilizing multi-bit flip-flops by clock synchronization. Diminishment of the clock power consumption with two single bit flip-flops are synchronized with single clock pulse. Uniting single bit flip-flops into one multi-bit flip-flop evades duplicate inverters, brings down the aggregate clock power utilization which lessens the total area. A mixture table is fabricated to acquire a multi-bit flip-flop which can store the flip-flops that can be consolidated. This task concentrates on D flip-flop which builds the loading of the clock signal. QCL adder is utilized as an application for multi-bit flip-flop. Highest ‘1’ bit finding algorithm is utilized to discover the highest 1 bit from the yield of QCL adder. This calculation checks the yield of QCL adder in each one cycle.

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Power Reduction In Vlsi Systems By Using Multi-Bit Flip-Flops

December 4, 2014