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Exploiting Self Reverse Bias Technique for Low Power SRAM Design

Publication Date : 10/07/2015



Author(s) :

Mr. Rahul. A. Burange , Dr. G. H. Agrawal.


Conference Name :
4th International Conference on Recent Trends in Engineering & Technology(ICRTET-2015) July 2-4,2015 Organized by SNJB's KBJ College of Engineering,Chandwad,Nashik,Maharashtra,India



Abstract :

Gated Vdd is one of the techniques to reduce static power in CMOS circuits. Static power dissipation gets drastically reduced by having an extra NMOS transistor between Static RAM (SRAM) cell and ground. This paper exploits the stacking effect by adding multiple NMOS transistors between SRAM cell and ground to reduce the static power consumption further. We examine the effect on power by placing multiple NMOS transistors between SRAM cell and ground. Power analysis is carried out by applying different vectors to the NMOS stack. To reduce the delay added in the SRAM read/write operation as a result of NMOS stack we propose addition of extra transistor in parallel to NMOS stack that is of greater width then the transistors of NMOS stack. Simulation results show that static power gets reduced by approximately 33 % at the cost of 20% increase in area. Simulation results and power analysis of other blocks of SRAM are also presented at the end.


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