Call For Paper Volume:4 Issue:8 Aug'2017 |

Design the Full Adder Block for Optimization of PDP

Publication Date : 10/07/2015



Author(s) :

Neha K. Sancheti , Shubhangi S. Bachhav.


Conference Name :
4th International Conference on Recent Trends in Engineering & Technology(ICRTET-2015) July 2-4,2015 Organized by SNJB's KBJ College of Engineering,Chandwad,Nashik,Maharashtra,India



Abstract :

In early days the explosive growth in laptops, portable personal communication systems and the evolution of the lessening technology, the research effort in low-power microelectronics has been intensified and low-power VLSI systems have emerged as highly in demand. An adder is a critical component in systems like processor, memory design, arithmetic logic unit etc. Therefore careful design of these circuits improves the power consumption and other performance metrics of VLSI systems. The purpose of this work is to study the impact of different full adder cells layout in MICROWIND tool at 45nm technology. For analysis CMOS conventional 28T full adder and CMOS 24T mirror based full adders layout is implemented. For comparison the parameters like power dissipation, area, delay and PDP are used.


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