Call For Paper Volume:4 Issue:8 Aug'2017 |

Design of High Speed FFT using Vedic Mathematics

Publication Date : 01/07/2015



Author(s) :

Akshata R. , Kanchan Joshi , Prof. V.P. Gejji , Prof. B.R.Pandurangi.


Volume/Issue :
Volume 2
,
Issue 6
(07 - 2015)



Abstract :

Abstract - Multipliers are extensively used in FIR filters, Microprocessors, DSP and communication applications. For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. The need of low power and high speed Multiplier is increasing as the need of high speed processors are increasing. In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per the proposed architecture, for two 8-bit numbers; the multiplier and multiplicand, each are grouped as 4-bit numbers so that it decomposes into 4×4 multiplication modules. In this paper we have designed FFT using Vedic Mathematics. The coding is done in verilog and the FPGA synthesis is done using Xilinx library. Keywords– FPGA, Multiplier, Xilinx.


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Design of High Speed FFT using Vedic Mathematics

June 30, 2015