Call For Paper Volume:4 Issue:8 Aug'2017 |

ANALYSIS AND DESIGN OF LOW VOLTAGE LDO WITH CMOS SUPER SOURCE FOLLOWER

Publication Date : 01/06/2015



Author(s) :

S.Karthick , ANANDHAN C.


Volume/Issue :
Volume 2
,
Issue 6
(06 - 2015)



Abstract :

In this paper a low voltage, low drop-out (LDO) voltage regulator design is implemented using         250 nm Technology. Here the design of the Low Voltage LDO comprises of two stage Error Amplifier (EA), CMOS Source follower, Power Mosfet (Mp) and Feedback Network. The main purpose of the design is to operate in low Voltage i.e 1V. The drop voltage of this design is less than 100mv that is 0.081mv. The experimental result shows that the Quiescent current (Iq) is 0.8µA, Power dissipation is 80pW and the regulated output voltage is 0.919mV. This design is build using 22 number of transistors only. This is the best achievement of the design.


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ANALYSIS AND DESIGN OF LOW VOLTAGE LDO WITH CMOS SUPER SOURCE FOLLOWER

June 3, 2015