Call For Paper Volume:4 Issue:8 Aug'2017 |

Efficient IIR Notch Filter

Publication Date : 28/02/2015

Author(s) :

Ms. Tuhina Dhuware , Prof. Gouri Morankar.

Volume/Issue :
Volume 2
Issue 2
(02 - 2015)

Abstract :

Speed is of chief interest in this era so IIR filters are being designed using HDL languages. The basic second order tunable notch filter is implementable using the Field Programmable Gate Array (FPGA) at 2.4 GHz. Proper pipelining with the power of decomposition-2 over the basic structure of the second order tunable notch filter has to be applied to achieve high speed. The pipelined notch filter can be implementable on virtex-5 FPGA. Parallel computing fast adders and multipliers can be used for less delay and the less power consumption. Baugh Wooly multiplier and carry select adder are to be used to achieve less delay and high speed. In order to calculate multiplier coefficients a new simpler efficient method pascal’s triangle will be used.

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Efficient IIR Notch Filter

February 24, 2015