Call For Paper Volume:4 Issue:6 Jun'2017

Implementation of Processing Element for Modular Multiplier Using Static CMOS and Multiplexer Logic Circuit at 65nm

Publication Date : 25/11/2015



Author(s) :

Yamini Banjare , Vishal Moyal.


Volume/Issue :
Volume 2
,
Issue 11
(11 - 2015)



Abstract :

Many public key cryptographic algorithms require modular multiplication of very large operands as their core arithmetic operation. In this paper fast processing and low power consuming processing element of modular multiplier hardware is proposed. Proposed processing element is implemented of 4 bit in 65nm technology using static CMOS and multiplexer logic. The processing element designed using static CMOS logic consumes 1.2246uw power and multiplexer logic consumes 0.939uw with 1.2volt operating voltage and 1 fF capacitor. The number of transistor in static CMOS logic contains 58T and multiplexer logic contains is 42T. The multiplexer logic based processing element consumes 23% less power than the static CMOS


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Implementation of Processing Element for Modular Multiplier Using Static CMOS and Multiplexer Logic Circuit at 65nm

November 22, 2015