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VERIFICATION OF FOUR PORT ROUTER FOR NETWORK ON CHIP

Publication Date : 31/12/2014



Author(s) :

Kadgonda A Kupade.


Volume/Issue :
Volume 1
,
Issue 6
(12 - 2014)



Abstract :

The focus of this Paper is the actual implementation of Network Router and verifies the functionality of the four port router for network on chip using the latest verification methodologies, Hardware Verification Languages and EDA tools and qualify the IP for synthesis and implementation. This Router design contains three output ports and one input port, it is packet based Protocol. This Design consists Registers and FIFO. For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized time multiplexed approach was used. Compared to the provided software reference implementation, our direct-mapped approach achieves three orders of magnitude speedup, while our virtualized time multiplexed approach achieves one to two orders of magnitude speedup, depending on the network and router configuration


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VERIFICATION OF FOUR PORT ROUTER FOR NETWORK ON CHIP

December 27, 2014