Call For Paper Volume:4 Issue:8 Aug'2017 |

FPGA IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER FOR ASYNCHRONOUS DATA SAMPLING

Publication Date : 30/11/2014



Author(s) :

Yazhini.T , Senthil kumar.V.M.


Volume/Issue :
Volume 1
,
Issue 5
(11 - 2014)



Abstract :

Now a days power consumption plays a vital role in vlsi circuits. The growing market of mobiles, battery-powered electronic devices demands the design of electronic circuits with low power consumption.To design a low power circuit, energy efficiency from the clock element is an important issue.There are different technique for the energy efficiency. One technique for efficiency is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Double- edge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock. Therefore, power consumption in DETFF based circuit may be reduced. The DETFF designs provide the best performance not only in power but also in speed. Clock gating is another well-accepted technique to reduce the dynamic power of idle modules or idle cycles, like the power wasted by timing components during the time when the system is idle. Clock gating means disabling the clock signal when the input data does not alter the stored data. However, incorporating clock gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data sampling (i.e., a change in output between clock edges). In this paper are discussing two different methods to avoid asynchronous data sampling and implement this using universal shift register.


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FPGA IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER FOR ASYNCHRONOUS DATA SAMPLING

December 4, 2014